Universal Verification Methodology (UVM) standard
We all known as the Class Reference Manual and how it is effective in our sphere if activity but a lot of us do not know that this document is available with a highly advanced user guide and the open source called SystemVerilog base class library implementation. One of the benefits of this standard is that it contains all sorts of measures needed for improving the design, verification of information, portability of this information verification and the associated tools.
The main mission of UVM is to provide the unified requirement or in other words standard to advanced ways of verifying the productivity taking into consideration the active teams that are working and showing intentions in the sphere of multi-company design as well as verification. To accelerate all the associated processes, these design teams can use this Class Reference Manual as well as User Guide with open-source reference implementation. I talking about the UVM leverages features, we need to say that is based on UVM 1.0 Early Adopter (EA) release and combines the direct derivative of the Open Verification Methodology (OVM).
Thanks to these basic features, Accellera VIP TSC will be able to center on adding specific features that are contained in other general methodologies and by this way to meet all the functional requirements and to decrease the length of the standards development cycle. In general it is needed to be said that the UVM meets all the functional requirements and provides effective correction of known bugs and impalements the enhanced requests. Among all the advanced features of the UVM, you will be able to find a Phasing mechanism, a Register Package increasing the model component transaction connectivity and chatting.